The Cohera Co-Processor. A fourth kind of helper chip.
COHERA is a new hardware architecture: a co-processor that works beside the processors a computer already has, and takes on the work it does most efficiently.
Three helpers you already know. One you don’t.
Every computer has a main processor. Over fifty years, each new kind of work brought a new kind of helper chip that plugs in beside it. None replaced the others; they work side by side.
Can do anything, one step at a time. It runs the computer.
Thousands of simple workers doing the same thing at once. Built for graphics, then drafted into AI.
Built for the arithmetic of AI: Google’s TPU in its data centres, NPUs inside phones and laptops.
COHERA: the efficient one. A co-processor that works beside the others, not instead of them. It takes on the work it does most efficiently, so the whole system does more with the same electricity.
It runs on programmable silicon: commercially available chips configured to run the COHERA design. That means it can go into standard servers now, without waiting for a custom chip.
What we publish, and what we don’t. We publish what COHERA does, how we measure it, and every result with its date and label. How the Cohera Co-Processor gets its efficiency stays with us.
Same job. Same answers. The meter stops when the work is done.
Two ways of counting electricity, never mixed in one figure: whole board, where everything the development board draws is counted (one core against one core); and added energy, the extra electricity the work adds above idle, each chip on its own meter (the commercial-chip comparison).
Compared with a commercial chip.
NVIDIA’s GB10 is production silicon, measured in our lab on the same job. It is faster per chip than one COHERA engine running on a development board.
So we measured one COHERA engine, then calculated how many it would take to match the GB10’s speed, and how much electricity they would use.
Per answer, COHERA used about 6× less added energy than the GB10’s GPU. Matching the GPU’s speed would take about 15 COHERA engines. The multi-engine figure is a calculation from one measured engine; that chip has not been built yet.
This is our floor, not our ceiling.
Every COHERA speed and energy measurement on this site was made on a development board: a programmable chip far less efficient than custom silicon, with no custom chip built yet. And it still beats a modern NVIDIA chip on energy per answer.
Custom chips typically need about 12× less dynamic power than programmable ones.
Every result, with its date and its label.
- Measured on this workload.Image recognition: one model, 1,000 images, one answer key.
- This hardware.One COHERA engine on a development board; each rival on the same board, or on its own production chip.
- This result.735× less electricity per answer than a CPU core, counted for the whole board.
- Here’s what we know.Every result below, with its date and a RECORDED or ESTIMATE label.
- Here’s what we’re testing next.Speed and energy beside a production GPU on large AI language models; then pilots inside real data centers.
Same image-recognition job and answer key on the same development board, 14–16 September 2026.
Rival measured in our lab on 24 September 2026; the GB10 processor’s electricity is estimated from two published reviews. COHERA: one measured engine, counted as the extra electricity the work adds; the multi-engine chip is a calculation, not built yet ESTIMATE.
| Date | Comparison | Result | Counted as | Label |
|---|---|---|---|---|
| 23 Oct 2026 | One COHERA engine running a complete 8-billion-parameter language model by itself | all correctevery token it produced and every value it stored matched the reference | Correctness, not speed or energy | RECORDED |
| 14 Sep 2026 | One core against one core: a CPU core, same development board, same test | 735×less electricity per answer | Whole board | RECORDED |
| 14 Sep 2026 | One core against one core: a GPU core, same board, same test | 529×less electricity per answer | Whole board | RECORDED |
| 16 Sep 2026 | One core against one core: an AI-specialist NPU core, same board, same test | 3.5×less electricity per answer | Whole board | RECORDED |
| 3 Aug 2026 | AMD’s AI accelerator, as shipped and driven by AMD’s own software, same board and test | 111×less electricity per answer | Whole board | RECORDED |
| 24 Sep 2026 | NVIDIA’s GB10 graphics chip, production silicon, same model, test set and answer key; set out in writing before the run | about 6×less added energy per answer | Added energy, each chip on its own meter | RECORDED |
| 24 Sep 2026 | COHERA engines needed to match the GB10 graphics chip’s speed | 15 enginescalculated from one measured engine | Calculation; that chip is not built yet | ESTIMATE |
| 2 Sep 2026 | A COHERA card working beside a GPU running a 14-billion-parameter AI model | all correctevery result matched the certified reference | Correctness, not speed or energy | RECORDED |
Internal measurements on a specific AI inference workload, repeatable under the tested conditions and not representative of all workloads. Sources and conditions are listed for engineers at the foot of this page.
Where COHERA is now, and what comes next
- Measured today: COHERA engines on real hardware, running image recognition, compared with processor, GPU, AI-specialist and commercial chips.
- In progress: COHERA working beside a production GPU on large AI language models. A first run with a 14-billion-parameter model produced correct results (2 Sept 2026); speed and energy measurements come next.
- Next: pilots inside real data centers, to measure system-level gains on real workloads. Key benchmark details are being prepared for independent validation.
- In development: an analog form of COHERA for the lowest-power jobs.
For the engineers · sources and conditions
Four designs ran the same image-recognition model on one development board, 1,000 images checked against the same answer key (957/1000) on every batch, electricity read at the board’s 12 V input at 20 samples a second. The designs: the Cohera Co-Processor engine; an NPU core; a GPU core; and a CPU core. Each is one core. Run fingerprints (sha256, first twelve): Cohera Co-Processor 7da436e99069, GPU core 410232328880, CPU core 63e293cd3848 (14 September 2026), NPU core 7483ed79d97e (16 September 2026). Whole-board electricity per decision: Cohera Co-Processor 17.38 µJ, NPU core 60.87, GPU core 9,207, CPU core 12,784 µJ.
The commercial-chip comparison was measured on the NVIDIA GB10 in our lab on 24 September 2026 with the identical model, test set and answer key, every run reproducing 957/1000, and written down before the run: GB10 GPU, batches of 65,536, 8,570,747 decisions a second, 21.82 W above its idle on its own power sensor = 2.546 µJ per decision added. Cohera Co-Processor engine: 592,272 decisions a second and 0.4355 µJ per decision added above the board’s idle (recorded); engines needed = rival speed ÷ 592,272, rounded up (15 against the GPU), a calculation, not a built chip. The GB10 processor’s electricity cannot be measured on this machine; the demo estimates it from two published reviews (ServeTheHome; Jeff Geerling) and labels it ESTIMATE. Measuring points differ: the GPU is its own sensor, the Cohera Co-Processor is the 12 V board input.
AMD’s AI accelerator, two cores, as shipped and driven by AMD’s own software, on the same board and image-recognition test, our measurement of 3 August 2026: 111× whole board against that campaign’s COHERA figure. AI inference stage: on 2 September 2026 a COHERA card worked beside a GPU running a 14-billion-parameter AI model; every one of its results matched the certified reference; a correctness result, not a speed or energy result. Language-model stage: on 23 October 2026 one COHERA engine on programmable hardware in a data-centre server ran an open 8-billion-parameter language model on two jobs, a 256-token and a 4,000-token prompt, each followed by 32 generated tokens; every generated token and every stored intermediate value matched a reference run of the same model; a correctness result, not a speed or energy result.
Programmable versus custom chips (about 12× dynamic power): I. Kuon and J. Rose, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, 2007.